This invention addresses the problem of maintaining a modem receive clock in the proper position. It is especially suited for use in 201 modems which encounter pattern sensitivity problems because neither scrambling nor adaptive equalization is used.
The signalling method used in 201 modems consists of phase shift keying (PSK) to generate the known dibit pattern illustrated in FIG. 1. The transmitted spectrum of the four possible states is shown in FIG. 2A as spectral lines. Typical group delay characteristics of telephone lines with fixed compensation are shown in FIG. 2B relative to the transmitted spectrum and illustrate that the low frequency component of 00 state and the high frequency component of the 10 state will encounter the most severe delays. In a conventional 201 modem a long stream of "bad" patterns, i.e. 00 or 10 states, may cause the receive clock to shift to accomodate the shifted envelopes of these patterns due to the associated group delay. This will usually cause data errors to occur when good patterns, i.e. 11 and 01 states or random data including these states, are transmitted. Such errors are generated because the receive clock was shifted from the normal "correct" position in order to provide better detection of the bad(shifted) patterns and is thus not in the correct position when the good patterns resume.